• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a security unit that prevents illegal retrieval of data, the security unit comprising a unit for encrypting data according to instructions received by the security unit and a common register for storing both intermediate and final results of data encryption. It includes. A switching element operatively coupled to the register selectively outputs the contents of the register. The switching element is controlled to prevent external access to the intermediate result of encryption. Such a security unit may be particularly useful as part of a memory unit attachable to a recording / playback apparatus such as a digital audio recorder / player.
    公开号:KR20010006968A
    申请号:KR1020000018211
    申请日:2000-04-07
    公开日:2001-01-26
    发明作者:오카우에타쿠미；이시바시요시히토；사카모토유키히로；미즈노아사미；키하라노부유키；요코타테페이
    申请人:이데이 노부유끼；소니 가부시끼 가이샤；
    IPC主号:
    专利说明:

    Security unit for use in memory card
    The present invention relates to a security unit used in a memory unit and / or a data processing unit to prevent unauthorized retrieval of data stored in a memory or data processing unit.
    In a conventional nonvolatile memory such as an electrically erasable PROM (EEPROM), two transistors are used to store one bit of information. As a result, the memory area per bit becomes large, which limits the ability to consolidate memory. On the other hand, this problem has been solved in the recently developed flash memory in which one bit is stored using a single transistor according to the "all-bit-erase" method. In the near future, it is expected that flash memory will replace conventional recording media such as magnetic disks and optical disks in many applications.
    Memory cards or “memory sticks” based on flash memory attachable to or detachable from the card read / write section have been developed. With the emergence of this type of memory card, digital audio recording / playback units have been developed to use memory cards instead of conventional disc shaped media such as CDs (compact discs) or mini-discs.
    Audio recorders using a memory card as a recording medium generally use a data compression method that allows data to be stored at a relatively high quality for recording / reproducing. The encryption method is executed to protect the copyright of the music title recorded and played back in such an audio recorder. For example, the audio recorder is designed to determine whether the memory card is invalid, and therefore cannot be used with the recorder, through encryption techniques. In other words, the effective recorder and the effective memory card can be used together to decrypt the encrypted data. Encryption techniques can be used to protect the security of information stored on memory cards as well as copyright protection.
    Typical memory cards do not include encryption. Therefore, when recording confidential data on such a memory card, the data is encrypted on the "set" side, i.e., the device ("set"), in which the card is inserted and sets the data for recording. The encrypted data is then sent to the memory card for storage. If the encryption key is stored on the memory card, the data security of the card is compromised. On the other hand, if an encryption key is stored in a particular set, data originally encrypted by that set and recorded on the memory card cannot be encrypted by a set other than that particular set. Therefore, compatibility of the memory card is not maintained. In order to solve this problem, a system in which the set and the memory card each have an encryption function has been proposed, so that the set and the memory card are mutually authenticated. The memory card in this case is regarded as a "smart card" having a processing circuit for executing data encryption. In this way, both the security and the compatibility of the card can be maintained.
    The security unit having the above authentication and encryption function encrypts according to the Data Encryption Standard (DES). DES is a block encryption system that segments text into blocks and encrypts each block segment. Using DES, 64-bit input data is encrypted with a 64-bit key (in fact, a 56-bit key and 8-bit parity) and the 64-bit encrypted data is output. DES has four usage modes, one of which is Cipher Block Chaining mode. The CBC mode is a feedback type mode in which 64-bit text and preceding encrypted data (64 bits) are XORed and the result is input to the DES unit. In the initial state, since there is no encrypted data, an initialization vector is used. In addition, since data is exchanged between the set and the memory card, a random number (random number) is generated and added to the data.
    If the memory card has an internal security unit, the set sends instructions to the memory card, and the memory card mutually authenticates the set and the card by correspondingly by returning data including the encryption key. The encryption circuit of the memory card has a register, the contents of which are transmitted to the set in response to an instruction by the set. Another register may be required to store the intermediate result of the encryption process. For example, if there is only one encryption circuit, a register is provided to store an intermediate calculation result of the encryption process when the encryption process is executed several times. These registers are prohibited from external access. The intermediate calculation result is used to decrypt the encrypted data.
    Thus, two types of registers are provided for a memory card with an internal security unit. That is, an accessible register for storing data to be transmitted to the set in response to the command and an inaccessible register for storing the intermediate calculation result of the encryption process are provided. Thus, due to the two registers, the circuit size of the security becomes large. This hinders the function of increasing the integration of a security unit composed of IC chips. When the encryption process is executed several times, in order to remove the registers for temporarily storing the data, it is necessary to obtain the final data (encrypted data) almost simultaneously using a plurality of encryption circuits. In this case, the circuit scale also becomes large.
    Accordingly, it is an object of the present invention to provide a security unit capable of maintaining security even at a small circuit scale.
    Another object of the present invention is to provide a memory unit including a security unit having a small circuit scale.
    In all embodiments of the present invention, the security unit includes an encryption unit for encrypting data in accordance with an instruction received by the security unit, and a common register for storing both intermediate and final results of data encryption. The switching element operatively coupled to the register selectively outputs the contents of the register. The switching element is controlled to prevent external access to the intermediate result of encryption. The security unit is particularly useful as part of a memory unit attachable to a recording / playback device such as a digital audio recorder / player.
    The common register has the function of storing the intermediate and final results of the encryption process, so it is not necessary to use multiple registers for these functions. In addition, there is no need to use multiple encryption circuits. Therefore, the circuit scale of the security unit is reduced.
    The above-mentioned objects, additional objects, features, and advantages of the present invention will become apparent from the following detailed description, which will be described in connection with the accompanying drawings.
    1 is a diagram showing the overall configuration of a recorder / player and a memory card according to an embodiment of the present invention.
    2 is a diagram illustrating an internal structure of a secure memory card according to an embodiment of the present invention.
    3 is a diagram illustrating an internal structure of a non-secure memory card according to an embodiment of the present invention.
    4 illustrates a structure of a file system processing hierarchy of a flash memory according to an embodiment of the present invention.
    5 shows the format of the physical data structure of the flash memory.
    6 is a diagram showing the structure of a boot block of the flash memory;
    7 is a diagram showing the structure of boot and attribute information of a boot block of a flash memory;
    8A and 8B illustrate the relationship between content and keys.
    9 is a diagram referred to explain an encryption process in a recording operation.
    10 is a diagram referred to describe the authentication process.
    11 is a diagram to be referred to explain the encryption process in the recording operation.
    12 is a diagram referred to explain an encryption process in a reproduction operation.
    Fig. 13 is a diagram referred to for explaining the decryption process in the reproducing operation.
    Fig. 14 is a diagram referred to for explaining the operation of the interface disposed between the recorder and the memory card.
    Fig. 15 is a diagram referred to for explaining the operation of the interface disposed between the recorder and the memory card.
    16 is a table showing an example of a protocol command used in an embodiment of the present invention.
    17 and 18 are tables showing instructions used in embodiments of the present invention.
    19 is a schematic block diagram of a memory unit in accordance with the present invention.
    20 is a schematic block diagram showing the structure of a security block according to the present invention.
    Explanation of symbols on the main parts of the drawings
    1: Recorder / Player 2: Central Processing Unit (CPU)
    3: security block 4: operation button
    5: display device
    1 is a block diagram showing the structure of a digital audio recorder / player 1 according to an embodiment of the present invention. The digital audio recorder / player 1 records and plays back digital audio signals using a removable memory card (or Memory Stick ™ ). The recorder / player 1 is part of an audio system together with an amplification unit (not shown), a speaker (not shown), a CD player (not shown), an MD recorder (not shown), a tuner (not shown), and the like. The present invention is applicable to other audio sets. For example, recorder / player 1 is a portable device. The present invention is also applicable to a set top box for recording digital audio data propagated via satellite data communication, digital broadcasting, or the Internet. The present invention is also applicable to a system for recording / reproducing moving picture data and still picture data, rather than audio data. The system according to an embodiment of the present invention records and reproduces additional information such as images and texts in addition to digital audio signals.
    The recorder / player 1 has a central processing unit (CPU) 2, a security block 3, an operation button 4, and a display device 5. The security block 3, the operation button 4, and the display device 5 are connected to the CPU 2 via the bus 16. The security block 3 includes a Data Encryption Standard (DES) encryption circuit. Data such as a recording command, a reproduction command, and the like corresponding to the operation button 4 of the user is provided to the CPU 2 via the bus 16. Various information, the operation status of the recorder / player 1, etc. are displayed on the display device 5. The audio interface 6 is arranged between an external input / output and an internal audio encoder / decoder 7 which will be described in detail below.
    As described in detail later, the memory card 40 includes an IC having a flash memory (non-volatile memory) 42, a control block 41, a security block 52 (including DES encryption circuit), a communication interface, a register, and the like. Chip. The memory card 40 is detachable from the recorder / player 1. According to the embodiment, the recorder / player 1 is also compatible with memory that does not have an encryption function (i.e. security block 52).
    The audio encoder / decoder 7 encodes the digital audio data according to a high efficiency encryption method to be written to the memory card 40. The encoder / decoder 7 also decodes the encoded data read from the memory card 40. A high efficiency ATRAC3 format encoding method may be used, which is a variation of the Adaptive Transform Acoustic Coding (ATRAC) format used in MDs.
    In the ATRAC3 format, audio data sampled at 44.1 KHz and quantized to 16 bits is encoded with high efficiency. The minimum data unit of audio data to be processed is a sound unit ("SU"). A 1SU has 1024 sample data and has bits (1024 x 16 bits x 2 channels) compressed to hundreds of bytes of data. The duration of 1 SU is about 23 msec. In this high efficiency encryption method, the size of the compressed data is about 10 times smaller than the size of the original data. Compared to the ATRAC3 format used in MDs, the audio signal compressed and decompressed according to the ATRAC3 format does not degrade in audio quality.
    The analog input 8 provides the analog-to-digital (A / D) converter 9 with reproduction output signals of MD, tuner and tape. The A / D converter 9 converts the signal from the analog input 8 into a digital audio signal (sampling frequency = 44.1 KHz, number of quantization bits = 16), and converts the converted digital audio signal into the audio interface 6. To provide. The digital input 10 provides the audio interface 6 with digital output signals of MDs, CDs, digital broadcast signals, or network propagated audio data. The digital input signal is transmitted via an optical cable, for example. The audio interface 6 selects an input digital audio signal from the A / D converter 9 and the digital input 10 and provides it to the audio encoder / decoder 7.
    The audio encoder / decoder 7 encodes the input digital audio signal and provides it to the security block 3. The security block 3 encrypts the encoded data received from the audio encoder / decoder 7 in order to protect the copyright of the contents of the data (here, the digital audio signal). The security block 3 of the recorder / player 1 has a plurality of master keys and a storage key unique to each unit. In addition, the security block 3 has a random number generation circuit (not shown). When the memory card 40 with the security block 52 is attached to the recorder / player 1, the security block 3 of the recorder / player 1 determines whether the memory card 40 is valid (i.e., the memory). Card 40 is authenticated). After the security block 3 of the recorder / player 1 has an appropriate authentication memory card 40, the security block 3 of the recorder / player 1 and the security block 52 of the memory card 40 establish a session. Share the key.
    The encrypted audio data output from the security block 3 is provided to the CPU 2. The CPU 2 communicates with the memory card 40 via the bidirectional serial interface 11. In an embodiment, memory card 40 is attached to the attach / detach mechanism (not shown) of recorder / player 1. The CPU 2 writes encrypted data into the flash memory 42 of the memory card 40. The encrypted data is serially transmitted between the CPU 2 and the memory card 40.
    The CPU 2 reads the encrypted audio data from the memory card 40 via the memory interface 11 and provides it to the security block 3. The security block 3 decrypts the encrypted audio data. The decrypted audio data is provided to an audio encoder / decoder 7 which decodes the decrypted audio data. The output signal of the audio encoder / decoder 7 is provided to the D / A converter 12 via the audio interface 6. The D / A converter 12 converts the digital audio data into an analog audio signal and transmits the result through the output 13. The audio data received from the audio encoder / decoder 7 and the decrypted data received from the security block 3 are output as digital output signals via the outputs 14 and 15 and also via the interface 6.
    2 is a block diagram showing the internal structure of the memory card 40. As shown in FIG. The memory card 40 is a one chip integrated circuit (IC) having a control block 41, a security block 52, and a flash memory 42. As shown in FIG. 2, the bidirectional serial interface 11 disposed between the CPU 2 of the recorder / player 1 and the memory card 40 includes a clock line SCK for transmitting a clock signal transmitted with data; It consists of 10 lines including a status line SBS for transmitting a status signal, a data line DIO for transmitting data, an interrupt line INT, two GND lines, two VCC lines, and two reserve lines.
    Four of the 10 lines are clock line SCK, status line SBS, data line DIO, and interrupt line INT. Clock line SCK is used to transmit clock signals to synchronize data transfers. The status line SBS is used to transmit a status signal indicating the status of the memory card 40. The data line DIO is used to input and output commands and encrypted audio data. The interrupt line INT is used to transmit an interrupt request signal from the memory card 40 issue to the CPU 2 of the recorder / player 1. When the memory card 40 is attached to the recorder / player 1, an interrupt signal is generated. In another embodiment, the interrupt signal is sent over the data line DIO, in which case the interrupt line INT is grounded and not used.
    The serial / parallel and parallel / serial interface blocks (“S / P and P / S IF blocks”) 43 are the interface of the control block 41 coupled to the interface 11. The S / P and P / S IF block 43 converts serial data received from the recorder / player 1 into parallel data. In addition, the parallel data of the control block 41 is converted into serial data, and the serial data is provided to the recorder / player 1. In addition, the S / P and P / S IF blocks 43 separate the commands and data received via the data lines for accessing the flash memory 42 and for executing the encryption process.
    In other words, using the data line DIO, when a command is sent, data is sent. The S / P P / S IF block 43 determines by the code of the received command whether the received command and data are for accessing the flash memory 42 or for executing an encryption process. Corresponding to the determination result, the flash memory 42 access instruction is stored in the instruction register 44, and the data is stored in the page buffer 45 and the write register 46. The error correction code encoding circuit 47 is arranged in connection with the write register 46. The error correction code encoding circuit 47 generates a redundant code of the error correction code for data temporarily stored in the page buffer 45.
    Output data of the command register 44, page buffer 45, write register 46, and error correction code encoding circuit 47 are provided to a flash memory interface and sequencer ("memory IF and sequencer") 51. Memory IF and sequencer 51 are interfaces coupled to flash memory 42 and control the data exchanged between flash memory 42 and control block 41. For example, the data may be memory IF and sequencer 51. Is written to the flash memory 42 through the "
    Data read from the flash memory 42 is provided to the page buffer 45, the read register 48, and the error correction circuit 49 through the memory IF and the sequencer 51. The error correction circuit 49 corrects an error of data stored in the page buffer 45. Error correction data output from the page buffer 45 and data output from the read register 48 are provided to the S / P and P / S IF blocks 43, and the recorder / player 1 is connected through the serial interface 11. Is provided to the CPU 2.
    In order to protect the copyright of the contents (audio data compressed in the ATRAC3 format: ATRAC3 data) written to the flash memory 42, the security block 3 of the recorder / player 1 and the security block of the memory card 40 ( 52 together encrypt the content. The security block 52 has a buffer, a memory 53, a DES encryption circuit 54, a nonvolatile memory 55, and the like.
    As shown in FIG. 2, the configuration ROM 50 is disposed in the control block 41. The configuration ROM 50 stores version information of the memory card 40 and various kinds of attribute information. The memory card 40 has a write protect switch 60 operable by a user. When the switch 60 is placed in the write protect position, even if the recorder / player 1 sends an erase command to the flash memory 42, the data stored in the flash memory 42 is not erased. When the switch 60 is placed in the write unprotected position, the data stored in the flash memory 42 can be erased. The oscillator 61 generates a clock signal that is used as a timing reference for the processes executed in the memory card 40.
    The security block 52 of the memory card 40 has a plurality of authentication keys and a storage key unique to each memory card. The nonvolatile memory 55 stores an encryption or storage key that is inaccessible from the outside of the security block 52. The security block 52 has a random number generation circuit. Secure block 52 authenticates recorder / player 1 (which forms a dedicated system using a given data format) and shares the session key. The content key to encrypt the ATRAC3 data is encrypted with the session key and transmitted to the recorder / player 1 and the memory card 40 at issue. In addition to the security block 52 of the memory card 40, the security block 3 of the recorder / player 1 has a unique storage key for each set. Once the content is encrypted and stored in flash memory 42, the content key corresponding to the storage key is encrypted and stored with the encrypted content.
    3 shows a memory card 40 'that does not have an encryption function. In other words, the memory card 40 'is an insecure memory card. Unlike the memory card 40 of FIG. 2, the memory card 40 ′ does not have a security block 52. The remaining structure of the memory card 40 'is substantially the same as the memory card 40. In addition, the size and shape of the memory card 40 'is the same as that of the memory card 40. Since the recorder / player 1 of FIG. 1 is a secure recorder, the recorder / player 1 and the memory card 40 are mutually authenticated and a key is communicated therebetween. When the memory card 40 'of FIG. 3 is attached to the recorder / player 1, the recorder / player 1 is a memory card 40' that is a non-secure memory card and cannot be used with the recorder / player 1 To judge.
    There are several ways the recorder / player 1 determines the type of memory card attached thereto. As an example, when memory card 40 'is attached to recorder / player 1, a key is transferred from recorder / player 1 to memory card 40' for authentication. Since memory card 40 'does not send the correct response to recorder / player 1, recorder / player 1 determines that memory card 40' is not secure after the time-out time has elapsed. . As another example, when the memory card 40 or 40 'is attached to the recorder / player 1, identification information indicating whether the memory card is secure is recorded in a predetermined area (boot area) of the memory card. After reading this identification information, recorder / player 1 determines the type of memory card attached thereto.
    In addition to the recorder / player 1 shown in FIG. 1, a unit using an insecure memory card 40 'according to the present invention will be described. One example is a digital handy movie camera that records an image produced by a CCD (Charge Coupled Device) camera to a memory card 40 'and reproduces the image therefrom. As will be described later, according to an embodiment of the present invention, in order to improve the compatibility of the memory card 40, a non-secure device such as a digital handy movie camera is configured to record and reproduce data using the memory card 40. . That is, as described above, the S / P and P / S IF blocks 43 have a function of distinguishing commands and data for the flash memory 42 and the security block 52.
    According to the embodiment, the memory cards 40 and 40 'store data using a disk-like recording medium FAT (File Allocation Table) file system of a personal computer. The flash memory 42 has an IPL (Initial Program Load) area and a FAT zero root directory. The IPL area stores the address of the program loaded first in the memory of the recorder / player 1. The IPL area also stores various information of the flash memory 42. The FAT area stores data in association with a memory block of flash memory 42. That is, the FAT area stores values representing unused blocks, subsequent block numbers, bad blocks, and last blocks. The root directory stores directory entries (file attributes, updated date (year, month, day), start cluster, file size, etc.).
    In addition to the file management system defined in the format of the memory cards 40 and 40 ', file management information (track information management file) for music files can be defined. The track information management file is stored in the flash memory 42 using the user blocks of the memory cards 40 and 40 '. Therefore, even if the FAT of the memory card 40 or 40 'is damaged, the file can be recovered.
    The track information management file is generated by the CPU 2. When the power supply of the recorder / player 1 is turned on, the CPU 2 determines whether the memory card 40 or 40 'is attached to the recorder / player 1. When the memory card 40 or 40 'is attached to the recorder / player 1, the CPU 2 reads the boot block of the flash memory 42. According to the identification information of the boot block, the CPU 2 determines whether the attached memory card is a secure memory card.
    When the memory card 40 is attached (that is, secure type), the CPU 2 executes an authentication procedure. Other data read from the memory card 40 is stored in a memory (not shown) managed by the CPU 2. In the flash memory 42 of the used memory card 40 or 40 ', the FAT and the root direction are written before being shipped. When data is recorded, a track information management file is created. After the CPU 2 authenticates the memory card 40, the recorder / player 1 records or reproduces the encrypted ATRAC3 data file.
    When data is recorded, a recording command is issued corresponding to the operation of the operation button 4. The input audio data is compressed by the encoder / decoder 7. ATRAC3 data received from the encoder / decoder 7 is encrypted by the security block 3. The CPU 2 stores the encrypted ATRAC3 data in the flash memory 42 of the memory card 40. Then, the FAT and track information management file are updated. Each time the file is updated (i.e., audio data is recorded), the FAT and track information management file are rewritten to a memory controlled by the CPU 2. When the memory card 40 is detached from the recorder / player 1 or the power of the recorder / player 1 is turned on, the final FAT and track information management files are transferred from the memory to the flash memory 42 of the memory card 40. Is provided. In this case, each time audio data is recorded, the FAT and track information management file stored in the flash memory 42 are recreated. When the data is edited, the contents of the track information management file are updated.
    4 is a schematic diagram showing the hierarchy of file system processing of a computer system using the memory card 40 or 40 'as the storage medium. As shown, the top hierarchical level is the application processing layer. The application processing layer is followed by a file management processing layer, a logical address management layer, a physical address management layer, and a flash memory access layer. The file management processing layer is a FAT file system. The physical address is assigned to a separate block of flash memory 42 of memory card 40 or 40 '. The relationship between the block of flash memory 42 and its physical address does not change. The logical address is an address logically processed on the file management processing layer.
    5 shows the physical structure of data processed in flash memory 42 of memory card 40 or 40 '. In the flash memory 42, a data unit (called a segment) is divided into a predetermined number of blocks (fixed length). One block is divided into a predetermined number of pages (fixed length). In the flash memory 42, data is erased one block at a time. Similarly, the size of each page is the same. One block consists of page 0 to page m. One block has a storage capacity of 8 KB (kilobytes) or 16 KB, and one page has a storage capacity of 512B (bytes). If one block has a storage capacity of 8 KB, the total storage capacity of the flash memory 42 is 4 MB (512 blocks) or 8 MB (1024 blocks). If one block has a storage capacity of 16 KB, the total storage capacity of the flash memory 42 is 16 MB (1024 blocks), 32 MB (2048 blocks), and 64 MB (4096 blocks).
    One page consists of a data portion of 512 bytes and a redundant portion of 16 bytes. The first three bytes of the redundant portion are the overwrite portions that are rewritten each time data is updated. The first three bytes in succession include the block status area, page status area, and update status area. The remaining 13 bytes of the redundant portion are fixed data that depends on the content of the data portion. 13 bytes include management flag area (1 byte), logical address area (2 bytes), format spare area (5 bytes), distributed information error correction code (ECC) (2 bytes), and data ECC area (3 bytes). Bytes). The distributed information ECC area includes redundant data for error correction for the management flag area, logical address area, and format spare area. The data ECC area contains redundant data for error correction processing for data in the 512-byte area.
    The management flag area includes the system flag (1: user block, 0: boot block), conversion table flag (1: invalid, 0: table block), copy inhibit flag (1: copy allowed, 0: copy not allowed), access permission flag. (1: free, 0: no read).
    The first two blocks (blocks 0 and 1) are the boot blocks. Block 1 is a backup of block 0. The boot block is the top block that is not valid in the memory card 40 or 40 '. When memory card 40 or 40 'is attached to recorder / player 1, the boot block is accessed first. The remaining blocks are user blocks. Page 0 of the boot block includes a header area, a system entry area, and a boot and attribute information area. Page 1 of a boot block contains a prohibited block data area. Page 2 of the boot block includes a Card Information Structure (CIS) / Idenfity Driver Information (IDI) area.
    6 shows pages 0, 1 and 2 of the boot block. The boot block header (368 bytes) stores the boot block ID, the format version, and the number of valid entries in the boot block. The system entry (48 bytes) stores the start position of the forbidden block data, its data size, its data type, the data starting position of CIS / IDI, its data size, and its data type. The boot and attribute information includes memory card type (read only, rewrite, hybrid type), block size, number of blocks, total number of blocks, secure / non-secure, card production data (production date), and the like.
    FIG. 7 shows the structure of the boot and attribute information (96 bytes) shown in FIG. The boot and attribute information includes the type and type of memory card (read-only, read-write enable, two types of hybrids, etc.), block size, number of blocks, total number of blocks, secure / non-secure, production data (production date: year , Month, day). The recorder / player 1 uses the security type information (1 byte) to determine whether the memory card is secure. In Fig. 7, (* 1) denotes a data item that the recorder / player 1 reads and checks when a memory card is attached, and (* 2) denotes a production / quality control data item.
    The insulating film of the flash memory 42 is deteriorated every time data stored in the memory is rewritten. Therefore, the lifetime of the memory card 40 or 40 'is limited by the number of times the flash memory 42 is rewritten. Therefore, it is desirable to prohibit repetitive access to a specific storage area (block) of the flash memory 42. Thus, when data stored at a particular physical address is rewritten, the updated data is not written back to the same block. Instead, the updated data is written to the unused block. Therefore, after the data is updated, the relationship between the physical address and the logical address is changed. When this process (called a swapping process) is performed, repeated access to the same block is prohibited. In this way, the service life of the flash memory 42 is extended.
    Since the logical address corresponds to the data written to the block, even if the updated data is physically moved to another block, the same logical address is maintained in the FAT. The swapping process causes a change in the relationship between logical and physical addresses. In this way, the conventional table of translating logical addresses into physical addresses is changed accordingly when this swapping process is performed. With reference to the translation table, a physical address corresponding to the logical address specified by the FAT is obtained. In this way, the updated data is properly accessed using the same logical address.
    The logical address-physical address translation table is stored in the RAM by the CPU 2. However, if the storage capacity of the RAM is small, the logical address-physical address translation table can be stored in the flash memory 42. This table basically correlates logical addresses (2 bytes) arranged in ascending order with physical addresses (2 bytes). Since the maximum storage capacity of the flash memory 42 is 128 MB (8192 blocks), the 8192 addresses can be represented by 2 bytes. The logical address-physical address translation table is also proportional to the storage capacity of the flash memory. If the storage capacity of the flash memory 42 is 8 MB (two segments), two pages corresponding to the two segments are used for the logical address-physical address translation table. When the logical address-physical address conversion table is stored in the flash memory 42, one bit of the management flag of the redundant portion of each page indicates whether or not the associated block is stored in the logical address-physical address conversion table.
    Now, the security protection function will be described in more detail. First, in Figs. 8A and 8B, the relationship between the key and the content is shown. Each tune (or song) stored in flash memory 42 is called a track. 8A shows one track stored in flash memory 42. As shown in FIG. 8A, each track includes a key area (header) 101. The content key CK generated for each track (title) of the encrypted audio data is encrypted with the storage key Kstm unique to the memory card, and the resulting data is stored in the key area 101. DES is used in the encryption process for content key CK and storage key Kstm. DES (Kstm, CK) indicates that the content key CK is encrypted with the storage key Kstm. The coded value preferably has 64 bits consisting of 56 bits of data and 8 bits of error detected by Cyclical Redundancy Checking (CRC).
    Each track is divided into parts 102. The part key PK is recorded in each part. The track shown in FIG. 8A has one portion 102. Portion 102 is a set of blocks 103 (16 KB each). Each block 103 stores the block seed BK_SEED and the original vector INV. The partial key PK pairs with the content key CK to generate a block key BK for the encryption of the content. That is, BK = DES (CK (+) PK, BK_SEED) (56 bits + 8 bits) (where (+) represents exclusive OR). The original vector INV is the initial value for the encryption / decryption process for the block.
    8b relates to the content data in the recorder / player 1. The content key CK for each track of content is decrypted and the resulting data is re-encrypted with the recorder specific storage key Kstd. The re-encrypted data is stored in the key area 111. That is, the decryption process is indicated by IDES (Kstm, CK) (56 bits + 8 bits). The re-encryption process is indicated by DES (Kstd, CK) (56 bits + 8 bits). The partial key PK that generates the block key BK is recorded for each portion 112 of the content. Each block 113 of portion 112 stores the block seed BD_SEED and the original vector INV. Along with the memory card, the block key BK is represented by BK = DES (CK (+) PK, BK_SEED) (56 bits + 8 bits).
    Write operation to the memory card 40
    The encryption process used for recording (writing) of the recorder / player 1 will be described with reference to FIG. For convenience of description, in FIG. 9, parts similar to those of FIG. 1 have the same reference numerals, and description thereof will be omitted. In addition, the interface 11, bus 6, and control block 41 used for transferring data and commands between the recorder / player 1 and the components of the memory card 40 are shown in FIG. 9 and in the following description. Omitted. In FIG. 9, SeK is a session key shared between recorder / player 1 and memory card 40 by mutual authentication. In Fig. 9, reference numeral 10 'is a CD and is a source of a digital audio signal input to the digital input 10.
    When the memory card 40 is attached to the recorder / player 1, the recorder / player 1 determines whether the memory card 40 is a secure memory card as identification information of the boot area. Since the memory card 40 is a secure memory card, the recorder / player 1 and the memory card 40 are mutually authenticated.
    The mutual authentication process between the recorder / player 1 and the memory card 40 is described below with reference to FIG.
    After the write request signal is transmitted from the recorder / player 1 to the memory card 40, the recorder / player 1 and the memory card 40 are mutually authenticated again, which will be described in more detail in FIG. If the recorder / player 1 and the memory card 40 recognize each other as appropriate according to the mutual identification process, a key writing process to be described later in more detail with reference to Fig. 11 is executed. Otherwise, the write operation ends. When the key writing process is completed, audio data is encrypted and written to the memory card 40 by the CPU 2 via the interface 11.
    In Fig. 9, recorder / player 1 generates a random number for each track of data (tune) to be written and generates a corresponding content key CK according to each random number. The security block 3 of the recorder / player 1 encrypts the content key CK using the session key SeK. The recorder / player 1 outputs the encrypted content key CK to the memory card 40. The DES encryption / decryption circuit 54 of the security block 52 of the memory card 40 decrypts the encrypted content key CK and re-encrypts the decrypted content key CK using the storage key Kstm from the memory 55. . The memory card 40 outputs the re-encrypted CK to the recorder / player 1 (CPU 2). The recorder / player 1 (CPU 2) sets the re-encrypted content key CK in the key area 111 (shown in Fig. 8B) of each track. The recorder / player 1 generates a random number for each partial data area 112 (shown in Fig. 8B) of each track, and generates a partial key PK according to each random number. Each generated partial key PK is set in the corresponding partial data area 112 by the CPU 2.
    The temporary key TMK is generated by the recorder / player 1 for each partial data area 112 by executing XOR on the partial key PK and the content key CK as shown in the following formula (1). Generating a temporary key TMK is not limited to using the XOR function. You can also use other function operators, such as the simple AND operator.
    TMK = PK XOR CK ... (1)
    The recorder / player 1 generates a random number for each block 113 of each partial data area 112 and generates a block seed BK_SEED according to each random number. In addition, recorder / player 1 (CPU 2) sets the generated block sheet BK_SEED to an appropriate position in each corresponding block 113. The recorder / player 1 executes a MAC (Message Authentication Code) operation for generating a block key BK for each block 113 using the temporary key TMK and the block seed BK_SEED in Equation (2).
    BK = MAC (TMK, BK_SEED) ... (2)
    In order to generate the block key BK, a secret key can be used for the input of a secure hash algorithm (SHA-1), RIPEMD-160, or other one-way hash function to perform a non-MAC operation. Here, the one-way function f defines a function that is easy to calculate y = f (x) from x but difficult to find x from y. One-way hash functions are described in more detail in "Handbook of Applied Cryptography, CRC Press".
    The audio encoder / decoder 7 converts the digital audio signal input from the CD 10 'to the digital input 10 or the analog audio signal input to the analogue input 8 into a digital signal. The digital signal from (9) is compressed in accordance with the ATRAC3 format. The secure block 3 then encrypts the compressed audio data in Cipher Block Chaining (CBC) mode using the block key BK, where the CBC mode is in Federal Information Processing Standard (FIPS) PUB81 (DES MODES OF OPERATION). Defined data encryption mode.
    The recorder / player 1 adds a header to the encrypted audio data and outputs the result to the memory card 40. The memory card 40 writes the encrypted audio data and the header into the flash memory 42. In this way, the process of writing audio data from the recorder / player 1 to the memory card 40 is completed.
    Fig. 10 shows an authentication process executed between recorder / player 1 (SET1) and memory card 40 (MEMORY CARD). In step S1, the random number generator of the security block 52 of the memory card 40 generates a random number Rm and transmits this number and the serial number ID of the memory card 40 to the recorder / player 1.
    In step S2, recorder / player 1 receives Rm and ID to generate authentication key IKj according to relationship IKj = MAC (MKj, ID), where MKj is one of the master keys stored in security block 3. . The recorder / player 1 generates a random number Rd and a message authenticator MAC A (Message Authentication Code) having an authentication key, i.e., MAC (IKj, Rd // Rm // ID). Thus, the recorder / player 1 generates a random number Sd and transmits Rd // Sd // MAC A // j to the memory card 40.
    In step S3, the memory card 40 receives the data Rd // Sd // MAC A // j, retrieves the authentication key IKj from the security block 52 corresponding to j, and retrieves Rd, Rm, ID. MAC B is calculated using the authentication key IKj. If the calculated MAC B is equal to the received MAC A , the memory card 40 determines that the recorder / displayer 1 is valid (i.e., authorized). In step S4, the memory card 40 generates MAC C = MAC (IKj, Rm // Rd) and generates a random number Sm. Then, memory card 40 transmits Sm // MAC O to recorder / player 1.
    In step S5, recorder / player 1 receives Sm // MAC C from memory card 40. The recorder / player 1 calculates MAC D using IKj, Rm, and Rd. When the calculated MAC D is equal to the received MAC C , the recorder / player 1 determines that the memory card 40 is valid (i.e., authorized). In step S6, the recorder / player 1 designates MAC (IKj, Rm // Rd) as the session key SeK. In step S7, the memory card 40 designates MAC (IKj, Rm // Rd) as the session key SeK. If the recorder / player 1 and the memory card 40 are mutually authenticated, the session key SeK is shared between them. The session key SeK is generated each time authentication succeeds.
    Fig. 11 shows a key writing process when the recorder / player 1 (SET) records audio data in the flash memory 42 of the memory card 40 (MEMORY CARD). In step S11, the recorder / player 1 generates a random number for each track of the content and generates the content key CK. In step S12, the recorder / player 1 encrypts the content key together with the session key SeK and transmits the encrypted DES (SeK, CK) to the memory card 40.
    In step S13, the memory card 940 receives the data DES (SeK, CK) from the recorder / player 1 and decrypts the content key CK together with the session key SeK. The decryption process is indicated by IDES (SeK, DES (SeK, CK)). In step S14, the memory card 40 re-encrypts the encrypted content key CK together with the storage key Kstm from the memory 55 and transfers the re-encrypted content key DES (Kstm, CK) to the recorder / player 1. do.
    In step S15, the recorder / player 1 places the re-encrypted content key CK in the key area 111 for managing the corresponding data area 112, and the re-encrypted content key CK and the content are stored in the memory card 40. A formatting process is executed so that the flash memory 42 is written to the flash memory 42. In order to encrypt the content, as shown in Fig. 9 and Equation 11, the content key CK and the partial key PK are exclusive OR (XOR or AND). The result of the XOR operation is the temporary key TMK. The temporary key TMK is stored only in the security block 3. In this way, the temporary key TMK is not accessible from outside the security block 3. At the beginning of each block 113, a random number is generated as the block seed BK_SEED. The random number is stored in each partial data area 112. The recorder / player 1 encrypts the block seed BK_SEED and the temporary key TMK to obtain a block key BK. In other words, the relationship BK = (CK (+) PK, BK_SEED) is obtained. The block key BK is stored only in the security block 3. In this way, the block key BK is not accessible from outside the security block 3.
    In step S16, the recorder / player 1 encrypts the data of each partial data area 112 block by block together with the block key BK, and transmits the encrypted data and the data of the key area 111 to the memory card 40. FIG. do. In step S17, the memory card 40 records the encrypted data received from the recorder / player 1 and the data (header data) of the key area 111 in the flash memory 42.
    Read operation from memory card 40
    The decryption process for playing (reading) the recorder / player 1 will be described with reference to FIG. For convenience, in FIG. 12, the same parts as in FIG. 1 have the same reference numerals, and a description thereof is omitted. In addition, the interface 11, bus 6, and control block 41 used for transferring data and commands between the recorder / player 1 and the components of the memory card 40 are shown in FIG. 12 and in the following description. Omitted.
    The track of the desired data (tune) is transferred from the recorder / player 1 to the memory card 40. The recorder / player 1 and the memory card 40 perform mutual authentication as in the above description associated with FIG. If the recorder / player 1 and the memory card 40 recognize each other as appropriate according to the mutual identification process, a key writing process to be described later in more detail with reference to Fig. 11 is executed. Otherwise, the write operation ends. When the key writing process is completed, encrypted audio data is read by the CPU 2 from the memory card 40 to the recorder / player 1.
    Since mutual identification is performed between the recorder / player 1 and the memory card 40, the encrypted content key CK is appropriate only if the recorder / player 1 and the memory card 40 recognize each other as appropriate. It can be decrypted using SeK. Therefore, illegal theft of audio data can be easily prevented. Data read during the read operation is written by the write operation shown in FIG. Setting the content key CK and the partial key PK in each partial data area 112 and setting the block seed BK_SEED in each block 113 to write data to and read data from the corresponding data area 102. It is for. When step S6 of Fig. 10 is completed, the memory card 40 and the recorder / player 1 share the session key SeK. Reading audio data from the memory card 40 proceeds as follows.
    The memory card 40 specifies data in the partial data area 102 (FIG. 8A) corresponding to the read request signal and outputs audio data from the block 103 (FIG. 8A) of the specified partial data area 102 to the sound unit SUs. Outputs The memory card 40 also reads the corresponding area 101 (FIG. 8A) of the audio data and outputs the result to the recorder / player 1.
    The recorder / player 1 picks up the encrypted content CK from the data in the key area 101 and outputs it to the memory card 40. The DES encryption / decryption circuit 54 of the security block 52 of the memory card 40 decrypts the encrypted content key CK using the storage key Kstm stored in the memory 55 and converts the decrypted content key CK into the session key SeK. Re-encrypt using
    The memory card 40 outputs the re-encrypted content key CK to the recorder / player 1. Recorder / player 1 decrypts the re-encrypted content key CK from memory card 40 using session key SeK. The recorder / player 1 then XORs the decrypted content key CK and the partial key PK from the data of each partial data area 102 to obtain a temporary key TMK according to equation (3).
    TMK = PK XOR CK ... (3)
    The recorder / player 1 performs the MAC operation shown in Equation 4 below using the temporary key TMK and the block seed BK_SEED of each partial data area 102 to obtain the block key BK. The block key BK is retrieved for block 103 as shown below.
    BK = MAC (TMK, BK_SEED) ... (4)
    The security block 3 of the recorder / player 1 decrypts the audio data using the block key BK. In detail, the audio data is decrypted for every block 103 using the individually retrieved block key BK. Decryption is also executed in the same 16KB block 103 used for encryption. The audio encoder / decoder 7 expands the decrypted audio data according to the ATRAC3 system and outputs the decrypted signal via the digital output 14, or the D / A converter 12 outputs the analog audio signal. The signal is converted into a signal and the result is output through the analog output 13. Alternatively, ATRAC3 audio data from the security block 3 is output via the output 15. The audio encoder / decoder 7 extends the audio data into the sound unit SUs.
    FIG. 13 shows a decryption process when the recorder / player 1 plays an audio track stored in the flash memory 42 of the memory card 40. As shown in FIG. As in the write operation shown in Figs. 9 to 11, the session key SeK is shared between the recorder / player 1 and the memory card 40 after the recorder / player 1 and the memory card 40 are mutually authenticated.
    In step S21, the recorder / player 1 (SET) reads data from the memory card 40 (MEMORY CARD) and encrypts the encrypted content key (i.e., DES (Kstm, CK)) together with the storage key Kstm. Obtain the content (partial data area 102 of the desired track). The recorder / player 1 then sends the encrypted content key CK together with the storage key Kstm to the memory card 40.
    In step S22, the memory card 40 decrypts the content key CK (i.e., IDES (Kstm, DES (Kstm, CK)) together with the storage key Kstm. In step S23, the memory card 40 associates with the session key SeK. The content key decrypted together is encrypted and DES (SeK, CK) is sent to recorder / player 1.
    In step S24, the recorder / player 1 decrypts the content key together with the session key SeK. In step S25, the recorder / player 1 generates a block key BK together with the decrypted content key CK, the partial key PK, and the block seed BK_SEED. In step S26, the recorder / player 1 decrypts each encrypted partial data area 102 together with the block key BK in block units. The audio encoder / decoder 7 decodes the decoded audio data.
    Referring to the interface 11 shown in FIG. 2, FIG. 14 is a timing diagram of data read from the memory card 40. In a state other than state 0 (initial state), the clock signal used to synchronize data is transmitted over clock line SCK. When data is transmitted or received at the time of recorder / player 1 and memory card 40, the signal level of status line SBS is lowered. The initial condition is called state or state 0 (initial state). At timing t31, recorder / player 1 causes the signal level of status line SBS to become high (state 1).
    When the signal level of the status line SBS becomes high, the memory card 40 (S / P and P / S IF block 43) determines that state 0 has changed to state 1. In state 1, recorder / player 1 sends a read command to memory card 40 via data line DIO. In this way, the memory card 40 receives a read command. The read command is a protocol command called Transfer Protocol Command (TPC). As will be described in detail later, protocol commands specify the content of the communication and the length of the data that follows.
    At timing t32, after the command is sent, the signal level of status line SBS changes from high to low. In this way, state 1 is changed to state 2. In state 2, the process specified by the command received by the memory card 40 is executed. In fact, the data at the address specified by the read command is read from the flash memory 42 into the page buffer 45. During the process, a busy signal (high level) is sent to the recorder / player 1 via the data line DIO.
    At timing t33, after data is read from the flash memory 42 into the page buffer 45, the supply of the busy signal is stopped. A ready signal (low level) is output to the recorder / player 1 indicating that the memory card 40 is ready to transfer data in accordance with a read command.
    When recorder / player 1 receives the ready signal from memory card 40, recorder / player 1 determines that memory card 40 is ready to process a read command. At timing t34, recorder / player 1 causes the signal level of status line SBS to become high. In other words, state 2 changes to state 3.
    In state 3, the memory card 40 outputs the data read in the page buffer 45 to the recorder / player 1 via the data line DIO. At timing t35, after the read data is transferred, recorder / player 1 stops transmitting the clock signal through clock line SCK. The recorder / player 1 also changes the signal level of the status line SBS from high to low. In this way, state 3 changes to the initial state (state 0).
    When an interrupt process is to be executed due to a state change in the memory card 40 as at timing t36, the memory card 40 transmits an interrupt signal to the recorder / player 1 via the data line DIO. When recorder / player 1 receives an interrupt signal from data card DIO via memory line 40 in state 0, recorder / player 1 determines that the signal is an interrupt signal and executes a procedure corresponding to the interrupt signal. do.
    FIG. 15 is a timing diagram showing an operation in which data is written into the flash memory 42 of the memory card 40. As shown in FIG. In the initial state (state 0), the clock signal is not transmitted over the clock line SCK. At timing t41, recorder / player 1 changes the signal level of status line SBS from low to high. In this way, state 0 is changed to state 1. In state 1, memory card 940 is ready to receive a command. At timing t41, a write command is sent to the memory card 40 via the data line DIO, and the memory card 40 receives the write command.
    At timing t42, recorder / player 1 causes the signal level of status line SBS to change from high to low. In this way, state 1 is changed to state 2. In state 2, recorder / player 1 transfers write data to memory card 40 via data line DIO and memory card 40 stores the received write data in page buffer 45.
    At timing t43, recorder / player 1 causes the signal level of status line SBS to change from low to high. In this way, state 2 changes to state 3. In state 3, memory card 40 writes write data to flash memory 42, memory card 40 transmits a busy signal (high level) to recorder / player 1 via data line DIO, The recorder / player 1 transmits a write command to the memory card 40. Since the current state is state 3, the recorder / player 1 determines that the signal received from the memory card 40 is a state signal.
    At timing t4, memory card 40 stops outputting the busy signal and transmits a ready signal (low level) to recorder / player 1. When the recorder / player 1 receives the ready signal, the recorder / player 1 determines that the writing process corresponding to the write command is completed and stops transmitting the clock signal. At timing t45, recorder / player 1 changes the signal level of status line SBS from high to low. In this way, state 3 returns to state 0 (the initial state).
    When recorder / player 1 receives a high level signal from memory card 40 via data line DIO in state 0, recorder / player 1 determines that the received signal is an interrupt signal. The recorder / player 1 executes a process corresponding to the received interrupt signal. When memory card 40 is detached from recorder / player 1, memory card 40 generates an interrupt signal.
    In addition to the read and write process in state 1, a command is sent. In state 2, data corresponding to the command is transmitted.
    The serial interface disposed between the recorder / player 1 and the memory card 40 is not limited to the interface 11 as described above. That is, various types of serial interfaces are used.
    16 is a table showing an example of a protocol command (TPC code) transmitted through the data line DIO of the serial interface. The data length of each protocol command is 1 byte. In FIG. 16, each protocol command is represented in hexadecimal (with suffix h) and decimal. In addition, the definitions of the individual protocol commands are displayed for both the non-secure memory card 40 '(FIG. 3) and the secured memory card 40 (FIG. 2). In Fig. 16, R and W represent a read protocol command and a write protocol command, respectively. As described above, since the command is sent in state 1 and the data is sent in state 2, the data length (in bytes) corresponding to each protocol command is displayed.
    Now, each of the protocol commands TPC will be described.
    TPC = 2Dh is an access command to the conventional flash memory (this command is simply referred to as a memory control command). This command is a page data read command and is commonly used for the memory cards 40 and 40 '. The data length following the command is the data length for one page (512 bytes + 2 bytes (CRC)). Page data is read from the page buffer 45.
    TPC = D2h is a memory control command. This command is a page data write command. The data length following the command is the data length for one page (512 bytes + 2 bytes (CRC)). The page data is written to the page buffer 45.
    TPC = 4Bh is a memory control command. This command is a read command for the read register 48. The data length following the command is (31 bytes + 2 bytes (CRC)).
    TPC = B4h is a memory control command. This command is a write command to the write register 46. The data length following the command is (31 bytes + 2 bytes (CRC)).
    TPC = 78h is a memory control command. This command is a command for reading one byte from the read register 48. The data length following the command is (1 byte + 2 bytes (CRC)).
    TPC = 87h is a memory control command. This command is a command for changing the access range of the command register 44. The data length following the command is (4 bytes + 2 bytes (CRC)).
    TPC = 1Eh is a data read command for the status register of the security block 52 of the memory card 40. However, this command is not defined for the memory card 40 '. The data length following the command is (2 bytes + 2 bytes (CRC)). The dedicated command for the security block 52 is called a security command.
    TPC = E1h is a memory control command. This command is a command setting command for the command register 44. The instruction following this instruction has a lower hierarchical level than the TPC instruction. Therefore, the data length of this command is (1 byte + 2 bytes (CRC)).
    TPC = 3Ch is a secure data read command for the security block 52 of the memory card 40. However, this command is not defined for the memory card 40 '. The data length following the command is (24 bytes + 2 bytes (CRC)).
    TPC = C3h is a secure data write command for the security block 52 of the memory card 40. However, this command is not defined for the memory card 40 '. The data length following the command is (26 bytes + 2 bytes (CRC)).
    17 and 18, an instruction (1 byte) followed by the TPC = F1h instruction is described. 17 shows commands for the non-secure memory card 40 '. These are as follows:
    E1h = AAh: Block read command
    E1h = 55h: block write command
    E1h = 33h: Block read / write cancel command
    E1h = 99h: block erase command
    E1h = CCh: Command to stop memory operation
    E1h = 5Ah: Power Save Mode Command
    E1h = C3h: Clear Page Buffer (Clear) command
    E1h = 3Ch: memory controller reset command
    18 shows instructions for a secure memory card 40. The definition of the command AAh shown in FIG. 18 (3Ch) is the same as the definition shown in FIG. That is, these commands are memory control commands defined in common to the memory cards 40 and 40 '. In Fig. 18, instructions 60h through 83h are security instructions for an encryption process (including decryption process and authentication process) dedicated to memory card 40.
    As shown in Figs. 17 and 18, memory control command TPCs common to the memory cards 40 and 40 'and security command TPCs dedicated to the memory card 40 are defined. Likewise, this relationship applies to commands at lower hierarchical levels. That is, at the lower hierarchical level, common memory control commands and security commands are defined. The security command is not defined (not used) for the memory card 40 '. According to an embodiment, when the S / P and P / S IF blocks 43 receive a command from the recorder 1 via the serial interface, the memory card 40 indicates that the received command TPC is a common memory control command or a security command. Determine the cognition. The memory card 40 transmits subsequent data to the appropriate circuit corresponding to the determination result. If the received command is, for example, a TPC = E1h command followed by another command, the memory card 40 sends the command to the appropriate circuit corresponding to the definition for the command shown in FIG.
    19 shows a configuration for selecting a circuit intended to transmit data in response to a received command. This configuration is implemented in the interface circuit 43 of the memory card 40. Data is transferred from the recorder 1 to the memory card 40 via the data line DIO. The received data is provided to terminal “a” of switch circuit 152 via delay circuit 150. In addition, the received data is provided to an input terminal of the detection circuit 151. The detection circuit 151 determines whether the protocol command TPC received through the data line DIO is a memory control command or a security command according to the code value of the protocol command. The switch circuit 152 is controlled according to the determination result. The delay circuit 150 compensates for the detection time of the detection circuit 151. These structural elements are made by hardware and / or software of the S / P and P / S IF block 43. According to the embodiment, since codes not used for the memory control command are assigned to the security command, the detection circuit 151 can easily determine these two types of commands.
    If the detection circuit 151 determines that the received protocol command is a memory control command, the terminal "a" of the switch circuit 151 is connected to the terminal "b". In this way, the memory control command is assigned to a page buffer (e.g., page buffer 45 shown in FIG. 2 but omitted in FIG. 19), a register (e.g., register 46 or 48 shown in FIG. 2) and the like. The terminals "a" and "b" of the switch circuit 151 are provided to control the flash memory 42. The data following the memory control command is provided to the page buffer, registers and the like. Alternatively, data is transferred from the page buffer, the register and the like to the recorder 1 via the terminals " a " and " b "
    If the detection circuit 151 determines that the reception protocol command is a security command, the terminal of the switch circuit 151 is connected to the terminal "c" of the switch circuit 151. The security command is provided to the security block 52 via terminals "a" and "c" of the switch circuit 151. Data following the security command is provided to the security block 52. Data is transmitted from the security block 52 to the recorder 1 via the terminals "a" and "c" of the switch circuit 151.
    If the received command is a protocol command (TPC = E1h), then a normal memory control command or a security command is followed. When the detection circuit 151 receives the TPC = E1h protocol command, the detection circuit 151 determines whether the control command or the security command is followed by the command. Then, the memory card 40 controls the switch circuit 151 according to the determination result. If the received command is not command TPC = E1h and is followed by a memory control command or security command, memory card 40 sends data to the appropriate circuit corresponding to the code value of the command.
    If the memory card 40 has a function of determining whether the received command is a memory control command or a security command, the memory card 40 can be used for a non-security type recorder. That is, the non-security type recorder does not exchange security information with the memory card 40. The non-security type recorder transmits only the write / read memory control command and the corresponding data to the memory card 40. As described above, the memory card 40 determines whether the command received from the recorder is a memory control command and writes / reads data corresponding thereto to / from the flash memory 42. In this way, data is written / read to / from memory card 40.
    In Fig. 20, an embodiment of the present invention will be described in more detail. 20 shows the structure of the security block 52 of the memory card 40 in detail. The security block 52 has a structure of a single chip IC together with the nonvolatile memory 42, the S / P and P / S IF blocks 43, the page buffer 45, and the like. As described above, the S / P and P / S IF block 43 and the security block 52 are connected. The structure of the security block 3 of the recorder 1 is the same as that of the security block 52 of FIG.
    In FIG. 20, reference numeral 110 is a DES encryption circuit having a key storage memory (nonvolatile). A register group 111 is provided that is coupled to the encryption circuit 110. The encryption circuit 110 executes the encryption process in the CBC mode, for example, and controls the switch circuits 112 and 113 to form a feedback loop. The contents of the write register 114 are provided to the register group 111 through the switch circuit 112. The contents of the register group 111 are stored in the read register 115.
    The read register 115 is connected to the register group 111 used in the encryption circuit 110. The intermediate calculation result of the encryption process is stored in the read register 115. Data written to the write register 114 is provided from S / P (serial-parallel) and P / S (parallel-serial) block 116. Data read from the read register 115 is provided to the IF block 43 via the S / P and P / S blocks 116. Write data is provided from the recorder 1 via the serial interface described above. The read data is provided to the recorder 1 via the serial interface.
    Security block 52 also includes an instruction register (CMD) 117 and a status register (STTS) 118. The security commands 60h-83h shown in FIG. 18 are transmitted from the recorder 1 to the memory card 40. The secure command is stored in the command register 117 via the IF block 43 and the S / P and P / S block 116. The command register 117 generates a command to be subsequently executed. The command stored in the command register 117 is a command to allow non-secret content to be read out from the read register 115. These commands are, for example, the 63h, 67h, and 6Dh commands shown in FIG. With these instructions, data encrypted by the encryption circuit 110 is transferred from the register group 111 to the read register 115. With a command to allow reading of non-secret data, read register 115 is read-enabled. In FIG. 20, the on / off states of the switch circuit 122 respectively indicate read enable / disable states.
    Status information stored in the status register 118 is transmitted to the recorder 1 via the S / P and P / S blocks 116 and the IF block 43. Security block 52 also has an instruction register 119 that stores the generated instructions. The security block 52 also has an increment block 120 that increments the command code, for example. In this way, the security block 52 continuously generates the command code. When the power of the memory card 40 is turned on (in the initial state), the command code of the internally generated command is 60h. Each time security block 52 executes one instruction, increment block 120 increments the instruction code by " + 1 " (such as 61h, 62h, 63h, ... 71h). When the memory card 40 is attached to the recorder 1, the command code increases from 60h to 71h to authenticate the memory card 40. Command codes 72h to 83h are used after the memory card 40 is authenticated. Command codes 72h to 83h are freely and repeatedly used unlike the commands used in the authentication process.
    The comparison circuit 121 compares the values stored in the two command registers 117 and 119. The comparison result of the comparison circuit 121 is stored in the status register 118. If the comparing circuit 121 determines that the command received from the recorder 1 (i.e., the contents of the command register 117) matches the command generated internally (i.e., the contents of the command register 119), a non-error A non-error state is set in the status register 118. Data representing the status is transmitted to the recorder 1. In this way, the operation of the recorder 1 continues. If the comparison result of the comparison circuit 121 indicates that these instructions are not matched, an error state is set in the status register 118. Data representing the status is transmitted to the recorder 1. In this way, the recorder 1 stops the operation. In addition, a message indicating the status is displayed. In this case, when the reset operation is executed, the comparison circuit 121 is initialized.
    According to an embodiment, the authentication commands may be executed only in a predetermined order. Therefore, even when the instructions 63h, 67h, 6Dh, and the like, which enable the read register 115, are provided for illegally reading the intermediate calculation result of the encryption process, the comparison result of the comparison circuit 121 is inconsistent. As shown, the operation of the recorder 1 is stopped. In this way, the intermediate calculation result of the encryption process is not illegally read.
    Although the security function according to the invention has been described in connection with the security unit 52 of the memory unit 40, it is noted that the invention can be applied to the security block 3 of the recorder 1 as well. In other words, some features of the security block 52 can be incorporated in the security block 3 of the recorder, in particular the function of making the intermediate calculation result unreadable. In addition, while DES has been described as a preferred encryption method, various other encryption methods may be used as an alternative method.
    In the foregoing description, embodiments of the present invention show advantages over the prior art. For example, in a security unit that executes an encryption process, one register performs both the function of storing the intermediate result of the encryption process and the additional function of storing the encrypted data, thus eliminating the use of two registers. do. In addition, since a plurality of encryption circuits are not required, the circuit scale of the security unit can be reduced. In addition, the registers are read-enabled only when non-secret data is stored in the registers using the command code, allowing the data to be accessed externally. That is, the internal calculation result of the confidentiality can prevent external access. In this way, security of confidential data is improved. Even if a command is received that allows the contents stored in the register to be read, the intermediate calculation result is inaccessible.
    The following claims are intended to cover all of the specific and specific features of the invention described herein, and to be equivalent to the description of the scope of the invention.
    权利要求:
    Claims (18)
    [1" claim-type="Currently amended] As a security unit,
    Encryption means for encrypting data in a predetermined order of externally generated instructions received by said security unit;
    Storage means for storing a final result of the encryption;
    A switching means operatively coupled to the storage means, for selectively outputting the contents of the storage means,
    Said switching means being controlled to prevent external access to an intermediate result of said encryption process stored in said storage means.
    [2" claim-type="Currently amended] The method of claim 1,
    Second storage means for storing an externally generated command received by the security unit,
    Said switching means being controlled to prevent access to the result of said encryption in accordance with an instruction stored in said second storage means.
    [3" claim-type="Currently amended] The method of claim 1,
    And detecting means for detecting whether the commands are received in the predetermined order.
    [4" claim-type="Currently amended] The method of claim 1,
    Command generating means for generating commands in the predetermined order;
    Comparison means for comparing an externally generated command with an instruction generated by said command generating means,
    And the security unit outputs an error signal if the compared commands do not match each other.
    [5" claim-type="Currently amended] A nonvolatile memory and a security unit for encrypting data in accordance with a command received in a predetermined order from outside of the security unit, wherein the encrypted data is a memory unit stored in the nonvolatile memory,
    The security unit,
    Storage means for storing a final result of the encryption;
    A switching means operatively coupled to the storage means, for selectively outputting the contents of the storage means,
    The switching means are controlled to prevent external access to intermediate results of the encryption process stored in the storage means.
    [6" claim-type="Currently amended] The method of claim 5,
    The security unit further comprises second storage means for storing an externally generated instruction received by the security unit,
    And said switching means is controlled to prevent access to the result of said encryption in accordance with a command stored in said second storage means.
    [7" claim-type="Currently amended] The method of claim 5,
    And the security unit further comprises detection means for detecting whether the commands are received in the predetermined order.
    [8" claim-type="Currently amended] The method of claim 5,
    The security unit,
    Command generating means for generating commands in the predetermined order;
    Comparison means for comparing the command received by the security unit with the command generated by the command generating means,
    And the security unit outputs an error signal if the compared instructions do not match each other.
    [9" claim-type="Currently amended] The method of claim 5,
    Interface means coupled to the nonvolatile memory and the security unit, the interface means for receiving external data provided to the memory unit and selectively providing the external data to the nonvolatile memory or the security unit.
    [10" claim-type="Currently amended] The method of claim 9,
    And the interface means receives an external command provided to the memory unit and provides data to the nonvolatile memory or the security unit in accordance with the external command.
    [11" claim-type="Currently amended] A method of encrypting data in accordance with instructions received in a predetermined order,
    Storing the final result of the encryption in storage means;
    Preventing access to intermediate results of said encryption stored in said storage means.
    [12" claim-type="Currently amended] The method of claim 11,
    Preventing the outputting of the final result of the encryption in response to the received command.
    [13" claim-type="Currently amended] The method of claim 11,
    Detecting whether the command has been received in the predetermined order.
    [14" claim-type="Currently amended] The method of claim 11,
    Generating instructions in the predetermined order;
    Comparing the received commands with the generated commands in a predetermined order;
    And outputting an error signal if the commands so compared do not match.
    [15" claim-type="Currently amended] The method of claim 11,
    And said storage means is a single register.
    [16" claim-type="Currently amended] As a security unit,
    An encryption unit for encrypting data in accordance with a command received by the security unit;
    A common register for storing both intermediate and final results of the data encryption;
    A switching element operatively coupled to the register, the switching element selectively outputting the contents of the register,
    The switching element is controlled to prevent external access to the intermediate result of encryption.
    [17" claim-type="Currently amended] A memory unit comprising a nonvolatile memory and a security unit for encrypting data in accordance with a received command,
    The encrypted data is stored in the nonvolatile memory, and the security unit is
    A common register for storing both intermediate and final results of the data encryption;
    A switching element operatively coupled to the register, the switching element selectively outputting the contents of the register,
    And the switching element is controlled to prevent external access to the intermediate result of encryption.
    [18" claim-type="Currently amended] A data processing unit comprising a security unit, the security unit comprising:
    An encryption unit for encrypting data in accordance with a command received by the security unit;
    A common register for storing both intermediate and final results of the data encryption;
    A switching element operatively coupled to the register, the switching element selectively outputting the contents of the register,
    The switching element is controlled to prevent external access to the intermediate result of encryption.
    类似技术:
    公开号 | 公开日 | 专利标题
    US9083512B2|2015-07-14|Recording device, and content-data playback system
    US8661553B2|2014-02-25|Semiconductor memory card and data reading apparatus, and data reading/reproducing apparatus
    US5392351A|1995-02-21|Electronic data protection system
    US6609116B1|2003-08-19|System and method for securely updating copy-protected media
    JP4649533B2|2011-03-09|Management device, editing device, audio data management system including recording medium, management device, editing device, recording medium, and method
    US7958366B2|2011-06-07|Information processing system
    EP1290610B1|2015-01-07|Recording medium, license management apparatus, and recording and playback apparatus
    US6851055B1|2005-02-01|Digital video recorder for encrypting/decrypting video programs in segments to facilitate trick play features
    JP4779183B2|2011-09-28|Playback apparatus and playback method
    JP5739925B2|2015-06-24|Record carrier
    CN1178140C|2004-12-01|Safety type memory equipment possessing enhanced compatibility
    JP4687703B2|2011-05-25|Recording system, information processing device, storage device, recording method, and program
    US8135133B2|2012-03-13|Digital data file encryption apparatus and method
    KR101973510B1|2019-05-09|Method, host apparatus and storage for protecting contents
    KR100737972B1|2007-07-12|Content provider system
    US6851063B1|2005-02-01|Digital video recorder employing a file system encrypted using a pseudo-random sequence generated from a unique ID
    US6347846B1|2002-02-19|Method and an apparatus to control copying from a data providing device to a data receiving device
    KR100911153B1|2009-08-06|Content data transmitting device and method, and recording/reproducing device
    KR100746771B1|2007-08-06|Method for reproducing an audio file in portable audio device
    KR101031951B1|2011-04-29|Secure porting of information from one device to another
    JP4219680B2|2009-02-04|System, method and device for playing recorded audio, video or other content from non-volatile memory cards, compact discs or other media
    US8098827B2|2012-01-17|Data processing system, data processing method, and program providing medium
    KR100718620B1|2007-05-16|Recording and reproducing apparatus
    KR100717656B1|2007-05-15|Storage medium, apparatus for storing data, apparatus for editing data, method for storing data and method for editing data
    US8156347B2|2012-04-10|Semiconductor memory card, playback apparatus, recording apparatus, playback method, recording method, and computer-readable recording medium
    同族专利:
    公开号 | 公开日
    CN1272027A|2000-11-01|
    MY128617A|2007-02-28|
    US6820203B1|2004-11-16|
    US20050060540A1|2005-03-17|
    EP1043860A2|2000-10-11|
    DE60038919D1|2008-07-03|
    US7124436B2|2006-10-17|
    EP1043860B1|2008-05-21|
    CN1197374C|2005-04-13|
    EP1043860A3|2005-09-14|
    KR100710603B1|2007-04-24|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1999-04-07|Priority to JP99-099947
    1999-04-07|Priority to JP9994799
    1999-06-24|Priority to JP99-178188
    1999-06-24|Priority to JP17818899
    2000-04-07|Application filed by 이데이 노부유끼, 소니 가부시끼 가이샤
    2001-01-26|Publication of KR20010006968A
    2007-04-24|Application granted
    2007-04-24|Publication of KR100710603B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP99-099947|1999-04-07|
    JP9994799|1999-04-07|
    JP99-178188|1999-06-24|
    JP17818899|1999-06-24|
    [返回顶部]